The code below is the top module for a CPU which uses the MIPS instruction set. This processor is capable of utilizing the following instructions:

For this particular model, the instruction set is given as an array of instructions, and given the 3-cycle delay should produce the correct values in the destination register. The memory system was not modeled in this implementation, but to simulate it I made a tristate buffer to use the memory ‘Databus’ as both an input and output.

For easier reading, I put all the submodules directly below the top module.

Skills

• Verilog
• MIPS
• Vivado
• Digital Hardware Design